1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor, and in particular, relates to a method for manufacturing a stacked capacitor for a dynamic random access memory (DRAM).
2. Description of the Related Art
Referring to FIGS. 1 and 2, a conventional method for manufacturing a stacked capacitor for a DRAM will be explained. The stacked capacitor is provided in a deep hole. The DRAM generally includes a memory cell array and a peripheral circuit region. FIG. 1 is a cross sectional view of a memory unit 100 of the conventional DRAM. The memory unit 100 includes two memory cells. A plurality of the memory unit 100 is arranged in a matrix array to form the memory cell array. The peripheral circuit region is provided in adjacent to the memory unit 100 via an element separation region 104. In the following explanation, explanation of the peripheral circuit region will be omitted.
The conventional memory unit 100 includes a switch portion 10, which includes two switching transistors, and a capacitor portion 20, which includes two stacked capacitors. The switch portion 10, which is provided on a p-type silicon substrate 101, includes an n-well 102, p-well 103 and the element separation region 104. The n-well 102 is provided on the p-type silicon substrate 101. The p-well 103 is provided on the n-well 102. The element separation region 104 is provided on the n-well 102 to be arranged in adjacent to the p-well 103. Another memory unit or the peripheral circuit region is provided in adjacent to the memory unit 100 via the element separation region 104.
The switching transistors are provided in the p-well 103. The switching transistors share a source 107 connected to a bit line 113. Each of the switching transistors includes a drain 106 and a gate electrode 109 as a word line. The drain 106 is connected to the capacitor portion 20. A gate insulating film is provided between the drain 106 and gate electrode 109. The gate electrode 109 has a polycide structure, in which a tungsten silicide film is stacked on a polycrystalline silicon film, or a polymetal structure, in which a tungsten film is stacked on a polycrystalline silicon film.
A first interlayer insulating film 114 is provided on the switching transistors (switching element). In the predetermined region of the first interlayer insulating film 114, there is provided a bit-line contact 112 to connect the source 107 and the bit line 113. The bit-line contact 112 is composed of polycrystalline silicon, titanium silicide, titanium nitride and tungsten films filled in a contact hole provided in the first interlayer insulating film 114. The bit line 113 is provided on the first interlayer insulating film 114. The bit line 113 is composed of tungsten nitride and tungsten films. For each drain 106, a contact 111 is provided in a predetermined region of the first interlayer insulating film 114. Each contact 111 is connected to each drain 106.
A second interlayer insulating film 201 is provided on the bit line 113 and the first interlayer insulating film 114. For each contact 111, a silicon plug 202 is provided in the second interlayer insulating film 201. Each silicon plug 202 is connected to each contact 111.
A silicon nitride film 203 is provided on the second interlayer insulating film 201. A third interlayer insulating film 204 is provided on the silicon nitride film 203. For each silicon plug 202, a deep hole is provided in a predetermined region of the silicon nitride film 203 and the third interlayer insulating film 204. For each deep hole, a lower electrode 205 is provided on the inner surface of the deep hole. Each lower electrode 205 is connected to each silicon plug 202. A dielectric 206 is provided on third interlayer insulating film 204 and each lower electrode 205. An upper electrode 207 is provided on the dielectric 206. Each of the capacitors, which include the lower electrode 205, dielectric 206 and upper electrode 207, is arranged in each deep hole in the silicon nitride film 203 and the third interlayer insulating film 204. The capacitors are stacked capacitors provided in the deep holes. An insulating film 401 is provided on the upper electrode 207. On the insulating film 401, provided is a wiring layer 402 composed of a titanium nitride film, an aluminum film and a titanium nitride film.
A portion of the upper electrode 207 is extended to the peripheral circuit region and is connected to the wiring layer 402 via a contact formed in a predetermined region of the insulating film 401.
As mentioned above, the formation of the interlayer insulating films, the formation of the contact, and the formation of the wiring layer are repeated as necessary to form the memory cell array and to form the DRAM.
For example, a technique related to the method for manufacturing a stacked capacitor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-026712).
In recent years, memory capacity of semiconductor device has been increased. As for DRAM, in particular, a gigabit class memory with the minimum processing dimension of 100 nm will be brought to the commercial stage. A DRAM corresponding to the minimum processing dimension of 90 nm or shorter is under development. In accordance with the miniaturization of elements as mentioned above, the permissible surface area of an electrode of a capacitor as a primary component of DRAM is inevitably reduced, resulting in a difficult situation of securing sufficient electrical capacity of the capacitor.
Under the above situation, a hemispherical silicon silicon plug 202 of polycrystalline silicon is formed in a predetermined position of the second interlayer insulating film 201 composed of silicon oxide. Next, the silicon nitride film 203 is formed on the second interlayer insulating film 201. Next, the third interlayer insulating film 204 of silicon oxide with a thickness of 3000 nm is formed on the silicon nitride film 203. Next, a hard mask 210 with a thickness of 500 nm is formed on the third interlayer insulating film 204. Next, a photoresist 211 is formed on the hard mask 210.
Referring to FIG. 2B, the pattern is formed in the hard mask 210 by lithography and dry etching.
FIG. 2C is a cross sectional view of the capacitor portion 20 in which a deep hole 500 is formed. The third interlayer insulating film 204 and the silicon nitride film 203 are etched by dry etching to form the deep hole 500. The hard mask 210 is used as the etching mask in the dry etching. In this dry etching, a bowing 502 is generated in the region slightly lower than the opening portion of the deep hole 500. The deep hole 500 has the maximum hole width B1 in the bowing 502. The maximum width B1 is larger than a width L1 of the opening in the hard-mask 210. Therefore a portion of the hard mask 210 and a portion of the third interlayer insulating film 204 in the vicinity of the hard mask 210 have an overhang structure 501.
For the dry etching of the third interlayer insulating film 204 as silicon oxide film, gas plasma such as C5F8, is used. The bonding between Si and O in the silicon oxide is cut by ions generated in the plasma. The resulting free Si reacts with F to form volatile SiF4. Then, SiF4 is removed. Thus, the etching proceeds. An etchant that mainly contributes to the etching is F ion. The F ion is accelerated by a potential difference between the plasma and the substrate generated by a self-bias of the plasma or an intentionally applied bias. The F ions fly into the opening in the hard mask 210 to form the deep hole 500 by etching the third interlayer insulating film 204. Most of F ions are incident on the third interlayer insulating film 204 perpendicularly to the substrate. However, an inclination is generated at the shoulder of the hard mask 210 in the course of the etching. When F ion is incident on the third interlayer insulating film 204 after recoil in the inclination, the F ion is incident on the third interlayer insulating film 204 obliquely to the substrate. Therefore, an increasing number of F ions are incident on the third interlayer insulating film 204 obliquely to the substrate as the etching proceeds. It is considered that the etching of the third interlayer insulating film 204 on the sidewall in the vicinity of the opening portion of the deep hole 500 results in the bowing. The bowing is not a significant problem for a conventional hole relatively shallow. However, the bowing is more significant problem when the hole is narrower for the miniaturization or when the hole is deeper for securing the sufficient electrical capacity.
Referring to FIG. 2D, the lower electrode 205 is formed on the third interlayer insulating film 204 to cover the upper surface of the third interlayer insulating film 204 and inside of the deep hole 500 after the removal of the hard mask 210. The photoresist 210 is filled in the deep hole 500 after the formation of the lower electrode 205.
Referring to FIG. 2E, a portion of the lower electrode 205, which covers the upper surface of the third interlayer insulating film 204, is removed to leave another portion of the lower electrode 205, which covers inside of the deep hole 500. Next, the photoresist 211 is removed.
Referring to FIG. 2F, the dielectric film 206 of the capacitor is formed on the upper surface of the third interlayer insulating film 204 and the another portion of the lower electrode 205. Next, the upper electrode 207 of the capacitor is formed on the dielectric film 206. There is the overhang structure 501 in the opening portion of the deep hole 500. The deep hole 500 has narrower hole width in the opening portion than the maximum hole width B1 in the bowing 502. Therefore, poor (uneven) coverage by the dielectric 206 is caused. The bowing 502 also cause a gap 503 in the middle of the deep hole 500.
As mentioned above, in the conventional method for manufacturing the stacked capacitor provided in the deep hole, the bowing 502 is necessarily generated when the deep hole 500 deeper than the conventional hole is formed by the anisotropic dry etching. When the bowing 502 is generated, the overhang structure 501 appears in the opening portion of the deep hole 500 and the hole width L1 in the opening portion is narrower than the hole width B1 in the bowing 502. As a result, in the succeeding processes, even if the upper electrode 207 is formed till the upper electrode 207 closes the opening portion of the deep hole 500, the gap 503 is generated in the deep hole 500. Consequently, the capacitor is extremely weak to mechanical stress. To be more specific, the capacitor is susceptible to the influence of a stress caused by the insulating film 401 in the process of forming the wiring layer 402 and a stress caused by a mold resin in a packaging process. Therefore, even if the characteristics of the capacitors satisfy the predetermined standard in a test performed immediately after the formation of the capacitors, there is a problem that a product yield is poor in a test performed after the packaging process and before shipping.
Moreover, in the process of forming the dielectric 206 of the capacitor, the overhang structure 501 where the opening portion of the deep hole 500 is narrow causes the poor coverage by the dielectric 206, resulting in a poor reliability of the capacitor.